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Table 19-2. UC3F Register Programming Model
0x2F C800
0x2F C804
0x2F C808
0x2F C80C
19.2.1.2 UC3F EEPROM Configuration Register (UC3FMCR)
The UC3F module configuration register is used to configure the operation and access
restrictions of the UC3F array and shadow row.
MSB
1
0
Field STOP LOCK
HRESET
0
1
16
17
Field
HRESET
0
0
Addr
1
Reset state determined by NVM registers. These bits will be set to 01 by the factory.
Figure 19-1. UC3F EEPROM Configuration Register (UC3FMCR)
Bits
Name
0
STOP
Array stop control. Writes to the STOP bit have no effect while in program or erase operation (SES
= 1). The STOP bit is always readable whenever the registers are enabled.
When STOP = 1, the reset state of STOP is 1 and the UC3F array is disabled; internal circuits are
switched into a low power state. The STOP bit may be used to implement low power standby
modes or power management schemes. The UC3FMCR remains readable and writable when
STOP = 1 so that the STOP bit may be deasserted. Attempts to program or erase the array while
STOP = 1 have no effect. SES cannot be set to 1 when STOP = 1.
When STOP = 0, the reset state of STOP is 0 and the UC3F array is enabled for accesses. All
registers that were disabled with STOP = 1 are now enabled. A STOP recovery time of 1 µs is
required for biases in the UC3F array to reach their appropriate states to resume normal operation.
Operations to the UC3F array should be delayed for at least 1µs after clearing the STOP bit.
0 = UC3F array is enabled
1 = UC3F array is disabled (low-power mode)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Address
2
3
4
—
FIC
SIE
ACCESS CENSOR
0
0
0
18
19
20
21
DATA
0
0
0
Table 19-3. UC3FMCR Bit Descriptions
Chapter 19. CDR3 Flash (UC3F) EEPROM
Register
Module Configuration (UC3FMCR)
Extended Module Configuration (UC3FMCRE)
High Voltage Control (UC3FCTL)
Reserved
5
6
7
8
9
1
1
0
1
1
1
1
22
23
24
25
0
0
0
1
1
0x2F C800
Description
Programming Model
10
11
12
13
14
SUPV
1
1
1
1
1
26
27
28
29
30
PROTECT
1
1
1
1
1
15
1
LSB
31
1
19-5
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