Motorola MPC533 Reference Manual page 612

QSMCM Global Registers
Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user accesses. The supervisor (SUPV) bit in the QSMCM module
configuration register (QSMCMMCR) designates the assignable data space as either
supervisor or unrestricted. If SUPV is set, then the space is designated as supervisor-only
space. Access is then permitted only when the CPU is operating in supervisor mode. If
SUPV is clear, both user and supervisor accesses are permitted. To clear SUPV, the CPU
must be in supervisor mode.
The QSMCM assignable data space segment contains the control and status registers for
the QSPI and SCI submodules, as well as the QSPI RAM. All registers and RAM can be
accessed on byte (8-bits), half-word (16-bits), and word (32-bit) boundaries. Word accesses
require two consecutive IMB3 bus cycles.
15.4 QSMCM Global Registers
The QSMCM global registers contain system parameters used by the QSPI and dual SCI
submodules for interfacing to the CPU and the intermodule bus. The global registers are
listed in Table 15-2.
1 MSB
Access Address
S 0x30 5000
T 0x30 5002
S 0x30 5004
S 0x30 5006
1
S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
2
8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries.
15.4.1 Low-Power Stop Operation
When the STOP bit in QSMCMMCR is set, the IMB3 clock input to the QSMCM is
disabled and the module enters a low-power operating state. QSMCMMCR is the only
register guaranteed to be readable while STOP is asserted. The QSPI RAM is not readable
in low-power stop mode. However, writes to RAM or any register are guaranteed valid
while STOP is asserted. STOP can be written by the CPU and is cleared by reset.
System software must bring each submodule to an orderly stop before setting STOP to
avoid data corruption. The SCI receiver and transmitter should be disabled after transfers
in progress are complete. The QSPI can be halted by setting the HALT bit in SPCR3 and
then setting STOP after the HALTA flag is set in SPSR.
15-6
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 15-2. QSMCM Global Registers
2
QSMCM Module Configuration Register (QSMCMMCR)
See Table 15-4 for bit descriptions.
QSMCM Test Register (QTEST)
Dual SCI Interrupt Level (QDSCI_IL)
See Table 15-5 for bit descriptions.
Reserved
MPC533 Reference Manual
Reserved
Queued SPI Interrupt Level (QSPI_IL)
See Table 15-6 for bit descriptions.
LSB
MOTOROLA