Motorola MPC533 Reference Manual page 1045

order to follow the rule that bypass appears only in the second field of compressed
instruction.
.
Msb
16-bit segment #1 – to be bypassed
2- to 9-bit TP1 for segment #2
4-bit class
The definition of the class includes:
• TP1 length=2-9
• TP2 length=11, 12, 13 or 14 indicating a 0, 10, 15 or 16 bit bypass, respectively.
• TP1 base address = base address of segment #1 vocabulary in RAM #1, if it exists
there
• TP2 base address = base address of segment #1 vocabulary in RAM #2, if it exists
there
• DS=1
• AS=0 or 1 directing access to the vocabulary in RAM #1 or RAM #2, respectively.
When the vocabulary is located in RAM #1, the class is referred to as CLASS_4band when
the vocabulary is located in RAM #2, the class is referred to as CLASS_4a. Refer to
Table G-2.
G.2.10 Instruction Layout Programming Summary
Table G-2 summarizes the programming for all possible compressed instruction layouts.
The un-compressed instruction of two half-words are referred as H1 & H2. The compressed
instruction can be built out of: (1) X1 field – representing a vocabulary pointer for encoding
of either H1 or H1+H2; (2) X2 field – representing a vocabulary pointer for encoding of
H2; and (3) BP – representing a bypass field.
Vocabularies V1 and V2 refer to the 16 Msb and 16 Lsb of the uncompressed instruction,
respectively.
G.2.11 Compression Process
The compression process is implemented by the following steps. See Figure G-11.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Uncompressed Instruction
16-bit segment #2 – to be compressed
Compressed Instruction
Figure G-10. CLASS_4 Instruction Layout
Appendix G. MPC534 Compression Features
Class-Based Compression Model Main Principles
0-, 10-, 15- or 16-bit bypass for segment #1
G-13