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Operating Environment Architecture (OEA)
3.15.4.4 Instruction Storage Exception (0x0400)
An instruction storage interrupt is never generated by the hardware. The software may
branch to this location as a result of an implementation-specific instruction storage
protection error exception.
3.15.4.5 External Interrupt (0x0500)
The external interrupt exception is taken on assertion of the internal IRQ line to the RCPU.
The interrupt may be caused by the assertion of an external IRQ signal, by a USIU timer,
or by an external chip peripheral. Refer to Section 6.1.4, "Enhanced Interrupt Controller,"
for more information on the interrupt controller.
The interrupt may be delayed by other higher priority exceptions or if the MSR[EE] bit is
cleared when the exception occurs. MSR[EE] is automatically cleared by hardware to
disable external interrupts when any exception is taken.
Upon detecting an external interrupt, the processor assigns it to the instruction at the head
of the history buffer (after retiring all instructions that are ready to retire).
The enhanced interrupt controller mode is available for interrupt-driven applications on
MPC533. It allows the single external interrupt exception vector 0x500 to be split into up
to 48 different vectors corresponding to 48 interrupt sources to speed up interrupt
processing. It also supports a low priority source masking feature in hardware to handle
nested interrupts more easily. See Section 6.1.4, "Enhanced Interrupt Controller," and
Chapter 4, "Burst Buffer Controller 2 Module."
The register settings for the external interrupt exception are shown in Table 3-28.
Table 3-28. Register Settings Following External Interrupt
Register
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
3-52
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Bits
1
All
Set to the effective address of the instruction that the processor would
have attempted to execute next if no interrupt conditions were present.
[0:15]
Cleared to 0
[16:31]
Loaded from bits [16:31] of MSR. In the current implementation, bit 30
of the SRR1 is never cleared, except by loading a zero value from
MSR[RI]
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN This bit is set according to (BBCMCR[EN_COMP] and
BBCMCR[EXC_COMP])
Other
Cleared to 0
MPC533 Reference Manual
Setting Description
MOTOROLA
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