Motorola MPC533 Reference Manual page 221

6.1.3 USIU General-Purpose I/O
The USIU provides 64 general-purpose I/O (SGPIO) pins (See Table 6-2). The SGPIO pins
are multiplexed with the address and data pins. In single-chip mode, where communicating
with external devices is not required, all 64 SGPIO pins can be used. In multiple-chip mode,
only eight SGPIO pins are available. Another configuration allows the use of the address
bus for instruction show cycles while the data bus is dedicated to SGPIO functionality. The
functionality of these pins is assigned by the single-chip (SC) bit in the SIUMCR. (See
Section 6.2.2.1.1, "SIU Module Configuration Register (SIUMCR).")
SGPIO pins are grouped as follows:
• Six groups of eight pins each, whose direction is set uniformly for the whole group
• 16 single pins whose direction is set separately for each pin
Table 6-2 describes the SGPIO signals, and all available configurations. The SGPIO
registers are described in Section 6.2.2.5, "General-Purpose I/O Registers."
SGPIO Individual
Group Name Pin Control
SGPIOD[0:7]
SGPIOD[8:15]
SGPIOD[16:23]
SGPIOD[24:31]
1
SGPIOC[0:7]
SGPIOA[8:15]
SGPIOA[16:23]
SGPIOA[24:31]
1
SGPIOC[0:7] is selected according to GPC and MLRC fields in SIUMCR. See Section 6.2.2.1.1, "SIU Module
Configuration Register (SIUMCR)."
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 6-2. SGPIO Configuration
Direction
Control
GDDR0
GDDR1
GDDR2
X SDDRD[23:31]
X SDDRC[0:7]
GDDR3
GDDR4
GDDR5
Chapter 6. System Configuration and Protection
System Configuration and Protection Features
Available Available
When SC = 00 When SC = 01
(32-bit Port (16-bit Port
Size Mode) Size Mode)
X
X
Available
Available
When SC = 10
When SC = 11
(Single-Chip
(Single-Chip
Mode with
Mode)
Trace)
X X
X X
X X
X X
X
X
X
6-7