Motorola MPC533 Reference Manual page 897

CPU Core
BKPT, TE,
VSYNC
DSCK
DSDI
Figure 21-6. Functional Diagram of MPC533 Debug Mode Support
The development port provides a full duplex serial interface for communications between
the internal development support logic of the CPU and an external development tool. The
development port can operate in two working modes: the trap enable mode and the debug
mode.
The trap enable mode is used in order to shift into the CPU internal development support
logic the following control signals:
1. Instruction trap enable bits, used for on the fly programming of the instruction
breakpoint
2. Load/store trap enable bits, used for on the fly programming of the load/store
breakpoint
3. Non-maskable breakpoint, used to assert the non-maskable external breakpoint
4. Maskable breakpoint, used to assert the maskable external breakpoint
5. VSYNC, used to assert and negate VSYNC
In debug mode the development port controls also the debug mode features of the CPU. For
more information Section 21.4, "Development Port."
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
ECR
DER
Development Port
Control Logic
9
TECR
Development Port
Shift Register
Chapter 21. Development Support
Development System Interface
SIU/
EBI
32
Internal
Bus
32
Development
DPIR
Port
DPDR
35
EXT
BUS
VFLS,
FRZ
Support
Logic
DSDO
21-27