Motorola MPC533 Reference Manual page 405

Table 10-6 shows the initial values of the "boot bank" in the memory controller.
Table 10-6. Boot Bank Fields Values After Hard Reset
10.8 Memory Controller External Master Support
The memory controller in the MPC533 supports accesses initiated by both internal and
external bus masters to external memories. If the address of any master is mapped within
the internal MPC533 address space, the access will be directed to the internal device, and
will be ignored by the memory controller. If the address is not mapped internally, but rather
mapped to one of the memory controller regions, the memory controller will provide the
appropriate chip select and strobes as programmed in the corresponding region (see
Section 6.2.2.1.3, "External Master Control Register (EMCR)").
The MPC533 supports only synchronous external bus masters. This means that the external
master works with CLKOUT and implements the MPC533 bus protocol to access a slave
device.
A synchronous master initiates a transfer by asserting TS. The ADDR[0:31] signals must
be stable from the rising edge of CLKOUT during which TS is sampled, until the last TA
acknowledges the transfer. Since the external master works synchronously with the
MPC533, only setup and hold times around the rising edge of CLKOUT are important.
Once the TS is detected/asserted, the memory controller compares the address with each
one of its defined valid banks to find a possible match. But, since the external address space
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Field
PS
SST
BL
WP
SETA
BI
V
AM[0:16]
ATM[0:2]
CSNT
ACS[0:1]
EHTR
SCY[0:3]
BSCY[0:2]
TRLX
Chapter 10. Memory Controller
Memory Controller External Master Support
Value (Binary)
RCW[4:5] BPS
0
0
0
0
0b1
CS[0] = ID[3]
CS[3] = ID[20] & ID[31]
0 0000 0000 0000 0000
000
0
00
0
0b1111
0b011
0
10-29