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Memory Map and Register Definitions
6.2.2.3.2
Software Service Register (SWSR)
The SWSR is the location to which the SWT servicing sequence is written. To prevent SWT
time-out, a 0x556C followed by 0xAA39 should be written to this register. The SWSR can
be written at any time but returns all zeros when read.
MSB
1
2
0
Field
Reset
Addr
Figure 6-27. Software Service Register (SWSR)
Bits
Name
SWT servicing sequence is written to this register. To prevent SWT time-out, a 0x556C followed
0:15
SWSR
by 0xAA39 should be written to this register. The SWSR can be written at any time but returns all
zeros when read.
6.2.2.3.3
Transfer Error Status Register (TESR)
The transfer error status register contains a bit for each exception source generated by a
transfer error. A bit set to logic 1 indicates what type of transfer error exception occurred
since the last time the bits were cleared by reset or by the normal software status
bit-clearing mechanism.
These bits may be set due to canceled speculative accesses
which do not cause an interrupt. The register has two identical
sets of bit fields; one is associated with instruction transfers and
the other with data transfers.
MSB
1
2
0
Field
Reset
16
17
18
Field
—
IEXT IBMT
Reset
Addr
Figure 6-28. Transfer Error Status Register (TESR)
6-40
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
4
5
6
0000_0000_0000_0000
0x2F C00E
Table 6-16. SWSR Bit Descriptions
NOTE
3
4
5
6
0000_0000_0000_0000
19
20
21
22
—
0000_0000_0000_0000
MPC533 Reference Manual
7
8
9
10
SWSR
Description
7
8
9
10
—
23
24
25
26
DEXT DBM
0x2F C020
11
12
13
14
11
12
13
14
27
28
29
30
—
MOTOROLA
LSB
15
15
LSB
31
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