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Clock
Address
TS
TA
CS
RD/WR
WE/BE
OE
Data
In Figure 10-14, notice the following:
• Because ACS = 0, TRLX being set does not delay the assertion of the CS and WE
strobes.
• Because CSNT = 1, WE/BE is negated one clock cycle earlier than normal. (Refer
to Figure 10-8).
• CS is not negated one clock cycle earlier, since ACS = 00.
• The total cycle length is three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— One extra clock cycle is required due to the effect of TRLX on the negation of
the WE/BE strobes.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figure 10-13. Relaxed Timing — Write Access
(ACS = 11, SCY = 0, CSNT = 1, TRLX = 1)
Chapter 10. Memory Controller
ACS =11
ACS=00 & CSNT = 1
CSNT = 1
Chip-Select Timing
10-17
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