Motorola MPC533 Reference Manual page 919

Bits Mnemonic
0:31 CMPA-D
Note: These registers are unaffected by reset.
21.6.3 Exception Cause Register (ECR)
The ECR indicates the cause of entry into debug mode. All bits are set by the hardware and
cleared when the register is read when debug mode is disabled, or if the processor is in
debug mode. Attempts to write to this register are ignored. When the hardware sets a bit in
this register, debug mode is entered only if debug mode is enabled and the corresponding
mask bit in the DER is set.
All bits are cleared to zero following reset.
MSB 1 2
0
Field — RST CHSTP
Reset
16 17 18
Field — SEE —
Reset
Addr
Bits Name
0 — Reserved
1 RST Reset interrupt bit. This bit is set when the system reset pin is asserted.
2 CHSTP Checkstop bit. Set when the processor enters checkstop state.
3 MCE Machine check interrupt bit. Set when a machine check exception (other than one caused by a
data storage or instruction storage error) is asserted.
4:5 — Reserved
6 EXTI External interrupt bit. Set when the external interrupt is asserted.
7 ALE Alignment exception bit. Set when the alignment exception is asserted.
8 PRE Program exception bit. Set when the program exception is asserted.
9 FPUVE Floating point unavailable exception bit. Set when the program exception is asserted.
10 DECE Decrementer exception bit. Set when the decrementer exception is asserted.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 21-20. CMPA-CMPD Bit Descriptions
Address bits to be compared
3 4 5
MCE — EXTI ALE PRE FPUVE DECE
0000_0000_0000_0000
19 20 21
ITLBER — DTLBER
0000_0000_0000_0000
Figure 21-16. Exception Cause Register (ECR)
Table 21-21. ECR Bit Descriptions
Chapter 21. Development Support
Description
6 7 8 9
22 23 24 25
—
SPR 148
Description
Development Support Registers
10 11 12 13 14
— SYSE TR
26 27 28 29 30
LBRK IBRK EBRK
15
FPASE
LSB
31
DPI
21-49