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Queued Serial Peripheral Interface
continues to shift one bit for each pulse of SCK. If PCS[0]/SS is negated before the proper
number of bits (according to BITS) is received, the next time the QSPI is selected it resumes
storing bits in the same receive-data segment address where it left off. If more than 16 bits
are transferred before negating the PCS[0]/SS, the QSPI stores the number of bits indicated
by BITS in the current receive data segment address, then increments the address and
continues storing as described above.
PCS[0]/SS does not necessarily have to be negated between
transfers.
Once the proper number of bits (designated by BITS) are transferred, the QSPI stores the
received data in the receive data segment, stores the internal working queue pointer value
in CPTQP, increments the internal working queue pointer, and loads the new transmit data
from the transmit data segment into the data serializer. The internal working queue pointer
address is used the next time PCS[0]/SS is asserted, unless the CPU writes to the NEWQP
first.
The DT and DSCK command control bits are not used in slave mode. As a slave, the QSPI
does not drive the clock line nor the chip-select lines and, therefore, does not generate a
delay.
In slave mode, the QSPI shifts out the data in the transmit data segment. The trans-mit data
is loaded into the data serializer (refer to Figure 15-1) for transmission. When the
PCS[0]/SS pin is pulled low the MISO pin becomes active and the serializer then shifts the
16 bits of data out in sequence, most significant bit first, as clocked by the incoming SCK
signal. The QSPI uses CPHA and CPOL to determine which incoming SCK edge the MOSI
pin uses to latch incoming data, and which edge the MISO pin uses to drive the data out.
The QSPI transmits and receives data until reaching the end of the queue (defined as a
match with the address in ENDQP), regardless of whether PCS[0]/SS remains selected or
is toggled between serial transfers. Receiving the proper number of bits causes the received
data to be stored. The QSPI always transmits as many bits as it receives at each queue
address, until the BITS value is reached or PCS[0]/SS is negated.
15.6.7
Slave Wraparound Mode
When the QSPI reaches the end of the queue, it always sets the SPIF flag, whether
wraparound mode is enabled or disabled. An optional interrupt to the CPU is gen-erated
when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wraparound
mode is enabled. A description of SPIFIE bit can be found in <Blue><bold>15.6.1.3 QSPI
Control Register 2 (SPCR2).
In wraparound mode, the QSPI cycles through the queue continuously. Each time the end
of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF, it remains set,
15-44
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
MPC533 Reference Manual
MOTOROLA
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