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MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB
0
Field
Reset
Addr
Figure 3-17. Machine Status Save/Restore Register 0 (SRR0)
When an exception occurs, SRR0 is set to point to an instruction such that all prior
instructions have completed execution and no subsequent instruction has begun execution.
The instruction addressed by SRR0 may not have completed execution, depending on the
exception type. SRR0 addresses either the instruction causing the exception or the
instruction immediately following. The instruction addressed can be determined from the
exception type and status bits.
3.9.7
Machine Status Save/Restore Register 1 (SRR1)
SRR1, SPR 27, saves the machine status on exceptions and restores the machine status
when an rfi instruction is executed.
MSB
1 2
3 4 5 6
0
Field
Reset
Addr
Figure 3-18. Machine Status Save/Restore Register 1 (SRR1)
In general, when an exception occurs, SRR1[0:15] are loaded with exception-specific
information, and MSR[16:31] are placed into SRR1[16:31].
3.9.8
General SPRs (SPRG0–SPRG3)
SPRG0–SPRG3, SPRs 272-275, are provided for general operating system use, such as
fast-state saves and multiprocessor-implementation support. SPRG0–SPRG3 are shown
below.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Undefined
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB
Undefined
Chapter 3. Central Processing Unit
SRR0
SPR 26
SRR1
SPR 27
OEA Register Set
31
31
3-27
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