Motorola MPC533 Reference Manual page 745

field CP. The prescaler overflow signal is used to clock the MMCSM up-counter. This
allows the MMCSMCNT to be incremented at the MCPSM output frequency divided by a
value between one and 256.
17.8.3 Modular I/O Bus (MIOB) Interface
• The MMCSM is connected to all the signals in the read/write and control bus, to
allow data transfer from and to the MMCSM registers, and to control the MMCSM
in the different possible situations.
• The MMCSM drives a dedicated 16-bit counter bus with the value currently in the
up-counter register
• The MMCSM uses the request bus to transmit the FLAG line to the interrupt request
submodule (MIRSM). A flag is set when an overflow has occurred in the up-counter
register.
17.8.4 Effect of RESET on MMCSM
When the RESET signal is asserted, only the FREN, EDGP, EDGN, and CLS bits in the
MMCSMSCR are cleared. The clock prescaler CP, PINC, and PINL bits in the same
register are not cleared.
• The PINC and PINL bits in the MMCSMSCR always reflect the state of the
appropriate external pins.
• The MMCSM is disabled after reset and must be explicitly enabled by selecting a
clock source using the CLS bits.
The MMCSMCNT and the MMCSMML, together with the clock prescaler register bits,
must be initialized by software, because they are undefined after a hardware reset. A
modulus value must be written to the MMCSMCNT (which also writes into the
MMCSMML) before the MMCSMSCR is written to. The latter access initializes the clock
prescaler.
17.8.5 MMCSM Registers
The privilege level to access to the MMCSM registers depends on the MIOS14MCR SUPV
bit. The privilege level is unrestricted after SRESET and can be changed to supervisor by
software.
MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14)
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MIOS14 Modulus Counter Submodule (MMCSM)
17-21