Motorola MPC533 Reference Manual page 888

Watchpoints and Breakpoints Support
Since bytes and half-words can be accessed using a larger data width instruction, it is
impossible to predict the exact value of the L-address lines when the requested
byte/half-word is accessed, (e.g., if the matched byte is byte two of the word and it is
accessed using a load word instruction), the L-address value will be of the word (byte zero).
Therefore, the CPU masks the two least-significant bits of the L-address comparators
whenever a word access is performed and the least-significant bit whenever a half-word
access is performed.
Address range is supported only when aligned according to the access size. (See
Section 21.2.1.3, "Examples")
21.2.1.3 Examples
• A fully supported scenario:
— Looking for:
Data size: Byte
Address: 0x00000003
Data value: greater than 0x07 and less than 0x0c
— Programming options:
One L-address comparator = 0x00000003 and program for equal
One L-data comparator = 0x00000007 and program for greater than
One L-data comparator = 0x0000000c and program for less than
Both byte masks = 0xe
Both L-data comparators program to byte mode
— Result:
The event will be correctly detected regardless of the load/store instruction the
compiler chooses for this access
• A fully supported scenario:
— Looking for:
Data size: half-word
Address: greater than 0x00000000 and less than 0x0000000c
Data value: greater than 0x4e204e20 and less than 0x9c409c40
— Programming option:
One L-address comparator = 0x00000000 and program for greater than
One L-address comparator = 0x0000000c and program for less than
One L-data comparator = 0x4e204e20 and program for greater than
One L-data comparator = 0x9c409c40 and program for less than
Both byte masks = 0x0
Both L-data comparators program to half-word mode
— Result:
21-18
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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