Motorola MPC533 Reference Manual page 1071

Table H-10. QSMCM A and B (Queued Serial Multi-Channel Module) (continued)
Address Access
0x30 502C – S/U
0x30 504A
0x30 504C – S/U
0x30 506A
0x30 506C – —
0x30 513F
0x30 5140 – S/U
0x30 517F
0x30 5180 – S/U
0x30 51BF
0x30 51C0 – S/U
0x30 51DF
0x30 5400 S
0x30 5402 T
0x30 5404 S
0x30 5406 S
0x30 540A S/U
0x30 540C S/U
0x30 540E S/U
0x30 5410 — —
0x30 5412
0x30 5414 S/U
0x30 5416 S/U
0x30 5418 S/U
0x30 541A S/U
0x30 541C S/U
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Symbol
SCTQ_A Transmit Queue Locations
SCRQ_A Receive Queue Locations
— Reserved
RECRAM_A Receive Data RAM
TRAN.RAM_A Transmit Data RAM
COMD.RAM_A Command RAM
QSMCM_B
QSMCMMCR_B QSMCM Module Configuration Register.
See Table 15-7 for bit descriptions.
QTEST_B QSMCM Test Register
QDSCI_IL_B Dual SCI Interrupt Level.
See Table 15-8 for bit descriptions.
QSPI_IL_B Queued SPI Interrupt Level.
See Table 15-9 for bit descriptions.
SCC1R1_B SCI1Control Register 1.
See Table 15-28 for bit descriptions.
SC1SR_B SCI1 Status Register.
See Table 15-29 for bit descriptions.
SC1DR_B SCI1 Data Register.
See Table 15-30 for bit descriptions.
— Reserved
PORTQS_B QSMCM Port QS Data Register.
See Section 15.5.1, "Port QS Data Register
(PORTQS)," for bit descriptions.
PQSPAR/ QSMCM Port QS PIn Assignment Register/
DDRQST_B QSMCM Port QS Data Direction Register.
See Table 15-14 for bit descriptions.
SPCR0_B QSPI Control Register 0.
See Table 15-17 for bit descriptions.
SPCR1_B QSPI Control Register 1.
See Table 15-19 for bit descriptions.
SPCR2_B QSPI Control Register 2.
See Table 15-20 for bit descriptions.
Appendix H. Internal Memory Map
Register Size Reset
16 S
16 S
— —
16 S
16 S
16 S
16 S
16 S
16 S
16 S
16 S
16 S
16 S
— —
16 S
16 S
16 S
16 S
16 S
H-13