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MIOS14 Double Action Submodule (MDASM)
Channel B is accessed via register B1. Register B2 is not accessible. Channels A and B
define respectively the leading and trailing edges of the PWM output pulse. The value in
register B1 is transferred to register B2 each time a match occurs on either channel A or B.
A FORCA or FORCB does not cause a transfer from B1 to B2.
The value loaded in register A is compared with the value on the 16-bit counter bus each
time the counter bus is updated. When a match on A occurs, the FLAG line is activated and
the output flip-flop is set. The value loaded in register B2 is compared with the value on the
16-bit counter bus each time the counter bus is updated. When a match occurs on B, the
output flip-flop is reset.
If both channels are loaded with the same value, when a
simultaneous match on A and B occurs, the submodule behaves
as if a simple match on B had occurred except for the FLAG
line which is activated. The output flip-flop is reset and the
value in register B1 is transferred to register B2 on the match.
The polarity of the PWM output signal is selected by the EDPOL bit. The output flip-flop
level can be obtained at any time by reading the PIN bit.
If subsequent compares occur on channels A and B, the PWM pulses continue to be output,
regardless of the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-flop
to the level corresponding to a comparison on A or B respectively. Note that the FLAG line
is not activated by the FORCA and FORCB operations.
Data registers A and B must be loaded with the values needed
to produce the desired PWM output pulse.
16-bit counter bus compare only occurs when the 16-bit
counter bus is updated.
Figure 17-20 provides an example of how the MDASM can be used for pulse width
modulation.
17-36
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
NOTE
WARNING
NOTE
MPC533 Reference Manual
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