Motorola MPC533 Reference Manual page 631

A maximum of 32 commands can be in the queue. These bytes are assigned an address from
0x00 to 0x1F. Queue execution by the QSPI proceeds from the address in NEWQP through
the address in ENDQP. (Both of these fields are in SPCR2.)
MSB 1
0
CONT BITSE
— —
CONT BITSE
Command Control
The PCS[0] bit represents the dual-function PCS[0]/SS.
Figure 15-17. CR[0:F] — Command RAM 0x30 51C0, 0x30 51DF
1
Bits Name
0 CONT Continue
0 Control of chip selects returned to PORTQS after transfer is complete.
1 Peripheral chip selects remain asserted after transfer is complete.
1 BITSE Bits per transfer enable
0 Eight bits
1 Number of bits set in BITS field of SPCR0.
2 DT Delay after transfer
0 Delay after transfer is 17 ÷ f
1 SPCR1 DTL[7:0] specifies delay after transfer PCS valid to SCK.
3 DSCK PCS to SCK Delay
0 PCS valid to SCK delay is one-half SCK.
1 SPCR1 DSCKL[6:0] specifies delay from PCS valid to SCK.
4:7 PCS[3:0] Peripheral chip selects. Use peripheral chip-select bits to select an external device for serial data
transfer. More than one peripheral chip select may be activated at a time, and more than one
peripheral chip can be connected to each PCS pin, provided proper fanout is observed. PCS0
shares a pin with the slave select (SS) signal, which initiates slave mode serial transfer. If SS is
taken low when the QSPI is in master mode, a mode fault occurs.
Refer to Section 15.6.5, "Master Mode Operation" for more information on the command
RAM.
15.6.3 QSPI Pins
Seven pins are associated with the QSPI. When not needed by the QSPI, they can be
configured for general-purpose I/O. Table 15-20 identifies the QSPI pins and their
functions. Register DDRQS determines whether the pins are designated as input or output.
The user must initialize DDRQS for the QSPI to function correctly.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3
DT DSCK
— —
DT DSCK
Table 15-19. Command RAM Bit Descriptions
Chapter 15. Queued Serial Multi-Channel Module
Queued Serial Peripheral Interface
4
PCS3 PCS2
—
PCS3 PCS2
Peripheral Chip Select
Description
.
SYS
5 6
PCS1
— —
PCS1
LSB
7
1
PCS0
—
1
PCS0
15-25