Motorola MPC533 Reference Manual page 884

Watchpoints and Breakpoints Support
Development
System OR
External
Peripherals
Maskable Breakpoint
Non-maskable Breakpoint
Development
Port
Development Port Trap Enable Bits
Software trap Enable Bits
LCTRL2
(Non-masked Control Bit)
MSRRI
MSR
Internal
Watchpoints
Watchpoints
Logic
X
bit wise AND
bit wise OR
X
Figure 21-2. Watchpoint and Breakpoint Support in the CPU
21.2.1 Internal Watchpoints and Breakpoints
This section describes the internal breakpoints and watchpoints support of the CPU. For
information on external breakpoints support refer to Section 21.3, "Development System
Interface."
Internal breakpoint and watchpoint support is based on eight comparators comparing
information on instruction and load/store cycles, two counters, and two AND-OR logic
structures. The comparators perform compare on the Instruction address (I-address), on the
load/store address (L-address) and on the load/store data (L-data).
The comparators are able to detect the following conditions: equal, not equal, greater than,
less than (greater than or equal and less than or equal are easily obtained from these four
conditions; for more information refer to Section 21.2.1.6, "Generating Six Compare
Types"). Using the AND-OR logic structures "in range" and "out of range" detections (on
address and on data) are supported. Using the counters, it is possible to program a
breakpoint to be recognized after an event was detected a predefined number of times.
21-14
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Internal
Peripherals
MPC533 Reference Manual
X
X
Counters
Breakpoint
to CPU
To Watchpoint
Pins
MOTOROLA