Motorola MPC533 Reference Manual page 1085

Appendix I
Clock and Board Guidelines
The MPC533 built-in PLL, oscillator, and other analog and sensitive circuits require that
the board design follow special layout guidelines to ensure proper operation of the chip
clocks. This appendix describes how the clock supplies and external components should be
connected in a system. These guidelines must be fulfilled to reduce switching noise which
is generated on internal and external buses during operation. Any noise injected into the
sensitive clock and PLL logic reduces clock performance. The USIU maintains a PLL
loss-of-lock warning indication that can be used to determine the clock stability in the
MPC533.
MOTOROLA Appendix I. Clock and Board Guidelines I-1
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE