Motorola MPC533 Reference Manual page 389

Clock
Address
WE/BE
OE
Data
Note: In this and subsequent timing diagrams in this section, the data bus refers to a read cycle. In a write cycle, the
data immediately follows TS.
Figure 10-8. Memory Devices Interface Basic Timing (ACS = 00, TRLX = 0)
10.3.2 Peripheral Devices Interface Example
Figure 10-9 illustrates the basic connection between the MPC533 and an external
peripheral device. In this case CSx is connected directly to the chip enable (CE) of the
memory device and the R/W line is connected to the R/W in the peripheral device. The CSx
line is the strobe output for the memory access.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
TS
TA
CS
MPC5xx
Address
CSx
RD/WR
Data
Figure 10-9. Peripheral Devices Interface
Chapter 10. Memory Controller
Chip-Select Timing
CSNT = 1, ACS = 00
Peripheral
Address
CE
RD/WR
Data
10-13