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Development Port
Mode Selection"
as the shift clock. These instructions or data are then transferred in
)
parallel to the CPU, the trap enable control register (TECR). When the processor enters
debug mode it fetches instructions from the DPIR which causes an access to the
development port shift register. These instructions are serially loaded into the shift register
from DSDI using DSCK (or CLKOUT) as the shift clock. In a similar way, data is
transferred to the CPU by moving it into the shift register which the processor reads as the
result of executing a "move from special purpose register DPDR" instruction. Data is also
parallel-loaded into the development port shift register from the CPU by executing a "move
to special purpose register DPDR" instruction. It is then shifted out serially to DSDO using
DSCK (or CLKOUT) as the shift clock.
21.4.6.2 Trap Enable Control Register
The trap enable control register is a 9-bit register that is loaded from the development port
shift register. The contents of the control register are used to drive the six trap enable
signals, the two breakpoint signals, and the VSYNC signal to the CPU. The "transfer data
to trap enable control register" commands will cause the appropriate bits to be transferred
to the control register.
The trap enable control register is not accessed by the CPU, but instead supplies signals to
the CPU. The trap enable bits, VSYNC bit, and the breakpoint bits of this register are
loaded from the development port shift register as the result of trap enable mode
transmissions. The trap enable bits are reflected in ICTRL and LCTRL2 special registers.
See Section 21.6.10, "L-Bus Support Control Register 2" and Section 21.6.10, "L-Bus
Support Control Register 2."
21.4.6.3 Development Port Registers Decode
The development port shift register is selected when the CPU accesses DPIR or DPDR.
Accesses to these two special purpose registers occur in debug mode and appear on the
internal bus as an address and the assertion of an address attribute signal indicating that a
special purpose register is being accessed. The DPIR register is read by the CPU to fetch
all instructions when in debug mode and the DPDR register is read and written to transfer
data between the CPU and external development tools. The DPIR and DPDR are pseudo
registers. Decoding either of these registers will cause the development port shift register
to be accessed. The debug mode logic knows whether the CPU is fetching instructions or
reading or writing data. If what the CPU is expecting and what the register receives from
the serial port do not match (instruction instead of data) the mismatch is used to signal a
sequence error to the external development tool.
MOTOROLA
Chapter 21. Development Support
21-37
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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