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Appendix J
Memory Access Timing
Table J-1 lists all possible memory access timings for internal and external memory
combinations. The clock values show the number of clocks from the moment an address is
valid on a specific bus, until data is back on that same bus. The following assumptions were
used when compiling the information:
• The arbitration time was ignored. The values assume that the bus (or buses) involved
in a transaction was in the IDLE state when the transaction needs that bus.
• The UIMB works in a mode of 1:1. This is relevant for IMB access values. In the
case of 2:1 mode, the clock latency for a cycle on the IMB should be doubled (each
IMB access takes two clocks).
• The basic delay of an external bus to a U-bus is four clocks (external master case).
• All IMB accesses are assumed to be 16-bit accesses only. If 32-bit accesses are used,
then each such IMB access is split into two separate 16-bit cycles with normal IMB
performance for each.
Table J-1. Memory Access Times Using Different Buses
RCPU Load/Store
RCPU Instruction Fetches 2-1-1-1-1..
Peripheral Mode
(only external master is
active)
Slave Mode
(both external and internal
CPUs are active)
1
"/" indicates on/off page Flash access.
2
N is the number of read cycle clocks from external address valid till external data valid. In the case of zero wait states,
N = 2.
3
Assuming BBC is parked on the U-bus
4
Until address is valid on external pins
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Internal Buses
Flash
RAM
DECRAM
1
3/4
1
3
3
2
4/5
6
6
5/6
7
6
Appendix J. Memory Access Timing
External RAM/Flash
Internal
Memory
IMB
SIU
Mapped
External
2
6
5
4+N
—
—
2+N
7
6
8
7
Show Cycle
Non-mapped
Internal
Write Read
Memory
4+N
2
2
4
2+N
—
1
J-1
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