Motorola MPC533 Reference Manual page 558

Programming the QADC64E Registers
Table 14-18. QADC64E_A Multiplexed Channel Assignments and Signal
Multiplexed Input Signals
Port Signal Analog
Name Signal Name
A_PQA[0] AN[52]
A_PQA[1] AN[53]
A_PQA[2] AN[54]
A_PQA[3] AN[55]
A_PQA[4] AN[56]
A_PQA[5] AN[57]
A_PQA[6] AN[58]
A_PQA[7] AN[59]
VRL Low Ref
1
VRH/ALTREF High Ref
— —
— —
— RESERVED
1
Whichever is selected in the CCW.
The channel field is programmed for channel 63 to indicate the end of the queue. Channels
60 to 62 are special internal channels. When one of the special channels is selected, the
sampling amplifier is not used. The value of V
onto the converter. Also for the internal special channels, programming any input sample
time other than two has no benefit except to lengthen the overall conversion time.
14.3.10 Result Word Table
The result word table is a RAM, 64 words long and 10 bits wide. An entry is written by the
QADC64E after completing an analog conversion specified by the corresponding CCW
table entry. Software can read or write the result word table, but in normal operation, the
software reads the result word table to obtain analog conversions from the QADC64E.
Unimplemented bits are read as zeros, and write operations do not have any effect. See
Figure 14-14 for a diagram of the result word table
While there is only one result word table, the data can be accessed in three different data
formats:
• Right justified in the 16-bit word, with zeros in the higher order unused bits
• Left justified, with the most significant bit inverted to form a sign bit, and zeros in
the unused lower order bits
• Left justified, with zeros in the lower order unused bits
14-34
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Designations (continued)
Other Functions /
Signal Type
Descriptions
MA[0] Input/Output
MA[1] Input/Output
MA[2] Input/Output
— Input/Output
— Input/Output
— Input/Output
— Input/Output
— Input/Output
—
—
(VRH – VRL)/2
End of Queue Code
—
RL
MPC533 Reference Manual
Channel Number in CCW CHAN
Binary
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
Input 0111100
Input 0111101
— 0111110
— 0111111
— 1011000 to
1111110
, V , or (V - V
RH RH RL
Field
Decimal
52
53
54
55
56
57
58
59
60
61
62
63
64 to 127
)/2 is placed directly
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