Motorola MPC533 Reference Manual page 478

Analog Subsystem
BUFFER
Sample
Time
2 cycles
QCLK
Sample TIME
13.4.1.2 Amplifier Bypass Mode Conversion Timing
If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass
(BYP) bit in the CCW, the timing changes to that shown in Figure 13-20.. The buffered
sample time is eliminated, reducing the potential conversion time by two QCLKs.
However, due to internal RC effects, a minimum final sample time of four QCLKs must be
allowed. This results in no savings of QCLKs. When using the bypass mode, the external
circuit should be of low source impedance, typically less than 10 kΩ. Also, the loading
effects of the external circuitry by the QADC64E need to be considered, since the benefits
of the sample amplifier are not present.
Because of internal RC time constants, a sample time of two
QCLKs in bypass mode for high frequency operation is not
recommended.
QCLK
Figure 13-20. Bypass Mode Conversion Timing
13-34
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Final Sample
Time
N cycles:
(2, 4, 8, 16)
Figure 13-19. Conversion Timing
Sample
Time
N cycles:
(2, 4, 8, 16)
Sample Successive Approximation Resolution
Time
MPC533 Reference Manual
Resolution
Time
10 cycles
Successive Approximation Resolution
Sequence
NOTE
Resolution
Time
10 cycles
Sequence
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