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Operating Environment Architecture (OEA)
Execution begins at physical address 0x0100 if the hard reset configuration word IP bit is
cleared to 0. Execution begins at physical address 0xFFF0 0100 if the hard reset
configuration word IP bit is set to 1.
3.15.4.2 Machine Check Exception (0x0200)
A machine-check exception is assumed to be caused by one of the following conditions:
• The accessed address does not exist.
• A data error was detected.
• A storage protection violation was detected by chip-select logic.
When a machine-check exception occurs, the processor does one of the following:
• Takes a machine check exception;
• Enters the checkstop state; or
• Enters debug mode.
Which action is taken depends on the value of the MSR[ME] bit, whether or not debug
mode was enabled at reset, and (if debug mode is enabled) the values of the CHSTPE
(checkstop enable) and MCIE (machine check enable) bits in the debug enable register
(DER). Table 3-26 summarizes the possibilities. When the processor is in the checkstop
state, instruction processing is suspended and cannot be restarted without resetting the core.
Table 3-26. Machine Check Exception Processor Actions
Debug Mode
MSR[ME]
Enable
0
1
0
0
1
1
An indication is sent to the SIU which may generate an automatic reset in this condition.
Refer to Chapter 7, "Reset," for more details.
The register settings for machine check exceptions are shown in Table 3-27.
3-50
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
CHSTPE
0
X
0
X
1
0
1
1
1
X
1
X
MPC533 Reference Manual
MCIE
Action Performed when Exception Detected
X
Enter checkstop state
X
Branch to machine-check exception handler
X
Enter checkstop state
X
Enter debug mode
0
Branch to machine-check exception handler
1
Enter debug mode
MOTOROLA
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