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Starting
Burst Order (Assuming
Address
ADDR[28:29]
word 0 → word 1 →
00
word 1 → word 2 → word 3
01
10
11
9.5.8.5
Transfer Size
The transfer size signals (TSIZ[0:1]) indicate the size of the requested data transfer. During
each transfer, the TSIZ signals indicate how many bytes are remaining to be transferred by
the transaction. The TSIZ signals can be used with BURST and ADDR[30:31] to determine
which byte lanes of the data bus are involved in the transfer. For non-burst transfers, the
TSIZ signals specify the number of bytes starting from the byte location addressed by
ADDR[30:31]. In burst transfers, the value of TSIZ is always 00.
9.5.8.6
Address Types
The address type (AT[0:3]), program trace (PTR), and reservation transfer (RSV) signals
are outputs that indicate one of 16 address types. These types are designated as either a
normal or alternate master cycle, user or supervisor, and instruction or data type. The
address type signals are valid at the rising edge of the clock in which the special transfer
start (STS) signal is asserted.
A special use of the PTR and RSV signals is for the reservation protocol described in
Section 9.5.10, "Storage Reservation." Refer to Section 9.5.14, "Show Cycle Transactions"
for information on show cycles.
Table 9-7 summarizes the pins used to define the address type. Table 9-8 lists all the
definitions achieved by combining these pins.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 9-5. 4 Word Burst Length and Order
Burst Length in
32-bit Port Size)
Words (Beats)
word 2 → word 3
word 2 → word 3
word 3
Table 9-6. BURST/TSIZE Encoding
BURST
TSIZ[0:1]
Negated
Negated
Negated
Negated
Asserted
Chapter 9. External Bus Interface
Burst Length
in Bytes
4
16
3
12
2
8
1
4
Transfer Size
01
Byte
10
Half-word
11
x
00
Word
00
Burst (16 or 32 bytes)
Bus Operations
Comments
BDIP never asserted
9-39
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