Motorola MPC533 Reference Manual page 369

External Master
1. Request Bus (BR)
2. Receives Bus Grant (BG) From Arbiter
3. Asserts Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
Figure 9-36. Basic Flow of an External Master Write Access
Figure 9-37, Figure 9-38 and Figure 9-39 describe read and write cycles from an external
master accessing internal space in the MPC533.
The minimum number of wait states for such access is two
clocks. The accesses in these figures are valid for both
peripheral mode and slave mode.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1. Drives Data
NOTE
Chapter 9. External Bus Interface
MPC5xx Device
1. Receives Address
Address in Internal
Memory Map
1. Receives Data
1. Asserts Transfer Acknowledge ( TA )
Bus Operations
No
Yes
Memory
Controller
Asserts CSx
If In Range
9-53