Motorola MPC533 Reference Manual page 714

Programmer's Model
Table 16-11. CANMCR Bit Descriptions (continued)
Bits Name
8 SUPV Supervisor/user data space. The SUPV bit places the TouCAN registers in either supervisor
or user data space.
0 Registers with access controlled by the SUPV bit are accessible in either user or
1 Registers with access controlled by the SUPV bit are restricted to supervisor mode
9 SELFWAKE Self wake enable. This bit allows the TouCAN to wake up when bus activity is detected after
the STOP bit is set. If this bit is set when the TouCAN enters low-power stop mode, the
TouCAN will monitor the bus for a recessive to dominant transition. If a recessive to dominant
transition is detected, the TouCAN immediately clears the STOP bit and restarts its clocks.
If a write to CANMCR with SELFWAKE set occurs at the same time a recessive-to-dominant
edge appears on the CAN bus, the bit will not be set, and the module clocks will not stop. The
user should verify that this bit has been set by reading CANMCR. Refer to Section 16.5.2,
"Low-Power Stop Mode" for more information on entry into and exit from low-power stop
mode.
0 Self wake disabled
1 Self wake enabled
10 APS Auto power save. The APS bit allows the TouCAN to automatically shut off its clocks to save
power when it has no process to execute, and to automatically restart these clocks when it
has a task to execute without any CPU intervention.
0 Auto power save mode disabled; clocks run normally
1 Auto power save mode enabled; clocks stop and restart as needed
11 STOPACK Stop acknowledge. When the TouCAN is placed in low-power stop mode and shuts down its
clocks, it sets the STOPACK bit. This bit should be polled to determine if the TouCAN has
entered low-power stop mode. When the TouCAN exits low-power stop mode, the STOPACK
bit is cleared once the TouCAN's clocks are running.
0 The TouCAN is not in low-power stop mode and its clocks are running
1 The TouCAN has entered low-power stop mode and its clocks are stopped
12:15 — Reserved. These bits are used for the IARB (interrupt arbitration ID) field in TouCAN
implementations that use hardware interrupt arbitration.
16.7.2 TouCAN Test Configuration Register
CANTCR — TouCAN Test Configuration Register
This register is used for factory test only.
16.7.3 TouCAN Interrupt Configuration Register (CANICR)
MSB 1
0
Field —
SRESET
Addr
Figure 16-10. TouCAN Interrupt Configuration Register (CANICR)
16-28
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
supervisor privilege mode
2 3 4 5
IRL
0000_0000_00
0x30 7484 (CANICR_B)
MPC533 Reference Manual
Description
6 7 8 9
ILBS
0x30 7482
10 11 12 13 14
—
00_1111
MOTOROLA
LSB
15