Motorola MPC533 Reference Manual page 1064

Table H-6. USIU (Unified System Interface Unit) (continued)
Address Access
0x2F C018 U
0x2F C01C U,
read only
0x2F C020 U
0x2F C024 U
0x2F C028 U
0x2F C038 U
0x2F C02C U
0x2F C030 U
0x2F C038 U
0x2F C03C U
0x2F C040 — U
0x2F C044
0x2F C048 — U
0x2F C04C
0x2F C050 — U
0x2F C054
0x2F C0FC — —
0x2F C0FF
H-6
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Symbol
SIEL Interrupt Edge Level Mask.
See Section 6.2.2.2.7, "SIU Interrupt Edge
Level Register (SIEL)" for bit descriptions.
SIVEC Interrupt Vector.
See Section 6.2.2.2.8, "SIU Interrupt Vector
Register (SIVEC)" for bit descriptions.
TESR Transfer Error Status Register.
See Table 6-17 for bit descriptions.
SGPIODT1 USIU General-Purpose I/O Data Register 1.
See Table 6-23 for bit descriptions.
SGPIODT2 USIU General-Purpose I/O Data Register 2.
See Table 6-24 for bit descriptions.
PDMCR2 Pads Module Configuration Register 2.
See Table 25-9 for bit descriptions.
SGPIOCR USIU General-Purpose I/O Control Register.
See Table 6-25 for bit descriptions.
EMCR External Master Mode Control Register.
See Table 6-13 for bit descriptions.
PDMCR2 Pads Module Configuration Register 2
See Table 25-9 for bit descriptions
PDMCR Pads Module Configuration Register.
See Table 2-5 for bit descriptions.
SIPEND2 — Interrupt Pending Registers 2 and 3.
SIPEND3 See Section 6.2.2.2.1, "SIU Interrupt Pending
Register (SIPEND)" for bit descriptions.
SIMASK2 — Interrupt Mask Register and Interrupt Mask
SIMASK3 Registers 2 and 3.
See Section 6.2.2.2.9, "Interrupt In-Service
Registers (SISR2 and SISR3)" for bit
descriptions.
SISR2 — SISR3 SISR2and SISR3 Registers.
See Section 6.2.2.2.9, "Interrupt In-Service
Registers (SISR2 and SISR3)" for bit
descriptions.
— Reserved
MPC533 Reference Manual
Register Size Reset
32 H
32 —
32 S
32 H
32 H
32 H
32 H
32 H
32 H
32 H
32 S
32 S
32 S
— —
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