Oea Register Set; Machine State Register (Msr) - Motorola MPC533 Reference Manual

OEA Register Set

Table 3-11. Time Base Field Definitions (Read Only)
Bits Name
0-31 TBU Time Base (Upper). The high-order 32 bits of the time base
32-63 TBL Time Base (Lower). The low-order 32 bits of the time base
In 32-bit MPC500 implementations such as the RCPU, it is not possible to read the entire
64-bit time base in a single instruction. The mftb simplified mnemonic copies the lower half
of the time base register (TBL) to a GPR, and the mftbu simplified mnemonic copies the
upper half of the time base (TBU) to a GPR.
3.9 OEA Register Set
The operating environment architecture (OEA) includes a number of SPRs and other
registers that are accessible only by supervisor-level instructions. Some SPRs are
RCPU-specific; some RCPU SPRs may not be implemented in other MPC500 processors,
or may not be implemented in the same way.
3.9.1

Machine State Register (MSR)

The machine state register is a 32-bit register that defines the state of the processor. When
an exception occurs, the contents of the MSR are loaded into SRR1, and the MSR is
updated to reflect the exception-processing machine state. The MSR can also be modified
by the mtmsr, sc, and rfi instructions. It can be read by the mfmsr instruction.
11
MSB 1
0
Field
HRESET
16 17 18
Field EE PR FP
HRESET 000
1
This bit is available only on code compression-enabled options of the MPC533.
2
The reset value is a reset configuration word value extracted from the internal bus line. Refer toSection 7.5.2, "Hard
Reset Configuration Word (RCW)."
3
The reset value is a reset configuration word value extracted from the internal bus line. But if the bits of BBCMCR
are changed upon SRESET, DCMPEN may have a different value than it would upon HRESET i.e. RCW.
Table 3-12 shows the bit definitions for the MSR.
3-22
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5
—
0000_0000_0000_0000
19 20 21 22
ME FE0 SE BE
U 0000_0
Figure 3-12. Machine State Register (MSR)
MPC533 Reference Manual
Description
6 7 8 9 10
23 24 25 26
FE1 — IP IR
2
ID(2)
11 12 13 14
POW 0
27 28 29 30
DR — DCMP RI
1
EN
3
000 ID(21) 00
MOTOROLA
15
ILE
LSB
31
LE