Motorola MPC533 Reference Manual page 209

Figure 5-1 shows the USIU block diagram.
USIU
U-Bus
Configuration Registers
• Software Watchdog
• Bus Monitor
• Periodic Interrupt
• Timer and Decrementer
• Real-time Clock
• Debug
• Pin Multiplexing
• Interrupt Controller
5.1 Memory Map and Registers
Table 5-1 is an address map of the USIU registers. Where not otherwise noted, registers are
32 bits wide. The address shown for each register is relative to the base address of the
MPC533 internal memory map. The internal memory block can reside in one of eight
possible 4 Mbyte memory spaces. See Figure 1-3 for details.
Address
0x2F C000
0x2F C004
0x2F C008
1
0x2F C00E
0x2F C010
MOTOROLA Chapter 5. Unified System Interface Unit (USIU) Overview
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
U-bus
Interface
Figure 5-1. USIU Block Diagram
Table 5-1. USIU Address Map
USIU Module Configuration Register (SIUMCR)
See Table 6-7 for bit descriptions.
System Protection Control Register (SYPCR)
See Table 6-15 for bit descriptions.
Reserved
Software Service Register (SWSR)
See Table 6-16 for bit descriptions.
Interrupt Pending Register (SIPEND).
Memory Control Lines
Memory
Controller
Address
Data
Slave
Interface
SGPIO
Register
Memory Map and Registers
E-Bus
E-bus
Interface
Clocks & RESET
5-3