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System Configuration and Protection Features
6.1.2
External Master Modes
External master modes are special modes of operation that allow an alternative master on
the external bus to access the internal modules for debugging and backup purposes. They
provide access to the internal buses (U-bus and L-bus) and to the intermodule bus (IMB3).
There are two external master modes. Peripheral mode (enabled by setting PRPM in the
external master control (EMCR) register) uses a special slave mechanism that shuts down
the RCPU and an alternative master on the external bus can perform accesses to any internal
bus slave. Slave mode (enabled by setting EMCR[SLVM] and clearing EMCR[PRPM])
enables an external master to access any internal bus slave while the RCPU is fully
operational. Both modes can be enabled and disabled by software. In addition, peripheral
mode can be selected from reset.
The internal bus is not capable of providing priority between internal RCPU accesses and
external master accesses. If the bandwidth of external master accesses is large, it is
recommended that the system force gaps between external master accesses in order to avoid
suspension of internal RCPU activity.
The MPC533 does not support burst accesses from an external master; only single accesses
of 8, 16, or 32 bits can be performed. The MPC533 asserts burst inhibit (BI) on any attempt
to initiate a burst access to internal memory.
The MPC533 provides memory controller services for external master accesses (single and
burst) to external memories. See Chapter 10, "Memory Controller," for details.
6.1.2.1
Operation in External Master Modes
The external master modes are controlled by the EMCR register, which contains the
internal bus attributes. The default attributes in the EMCR allow an external master to
configure the EMCR with the required attributes and access internal registers. The external
master must be granted external bus ownership in order to initiate the external master
access. The SIU compares the address on the external bus to the allocated internal address
space. If the address is within the internal space, the access is performed with the internal
bus. The internal address space is determined according to IMMR[ISB] (see
Section 6.2.2.1.2, "Internal Memory Map Register (IMMR)," for details). The external
master access is terminated by the TA, TEA, or RETRY signal on the external bus.
A deadlock situation might occur if an internal-to-external access is attempted on the
internal bus while an external master access is initiated on the external bus. In this case, the
SIU will assert the RETRY on the external bus in order to relinquish and retry the external
access until the internal access is completed. The internal bus will deny other internal
accesses for the next eight clocks in order to complete the pending accesses and prevent
additional internal accesses from being initiated on the internal bus. The SIU will also mask
internal accesses to support consecutive external accesses if the delay between the external
MOTOROLA
Chapter 6. System Configuration and Protection
6-5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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