Motorola MPC533 Reference Manual page 406

Memory Controller External Master Support
is shorter than the internal space, the actual address that is used for comparing against the
memory controller regions is in the format of: {00000000, bits [8:16] of the external
address}. In the case where a match is found, the controls to the memory devices are
generated and the transfer acknowledge indication (TA) is supplied to the master.
Because it takes two clocks for the external address to be recognized and handled by the
memory controller, the TS which is generated by the external master is ahead of the
corresponding CS and strobes which are asserted by the memory controller. This 2-clock
delay might cause problems in some synchronous memories. To overcome this, the
memory controller generates the MTS (memory transfer start) strobe which can be used in
the slave's memory instead of the external master's TS signal. As seen in Figure 10-20, the
MTS strobe is synchronized to the assertion of CS by the memory controller so that the
external memory can latch the external master's address correctly. To activate this feature,
the MTSC bit must be set in the SIUMCR register.
On the , when the external master accesses the internal flash when it is disabled, the access
is terminated with the transfer error acknowledge (TEA) signal asserted, and the memory
controller does not support this access in any way.
When the memory controller serves an external master, the BDIP signal becomes an input
signal. This signal is watched by the memory controller to detect when the burst is
terminated.
10-30 MPC533 Reference Manual MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE