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– a – analog input
– i – input only
– d – has direct connection to the pad (may be used for module test)
– r – resized cell instance
9. Column Descriptions:
– Columns 1 through 8 are entries from the boundary-scan description from the BSDL file. The columns
and formats for each of these entries are defined in the IEEE Std. 1149.1b-1994 Supplement to the
IEEE Std. 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture document.
Descriptions of these columns are described below:
– Column 1: Defines the bit's ordinal position in the boundary scan register. The shift register cell nearest
TDO (i.e., first to be shifted in) is defined as bit 0; the last bit to be shifted in is 519.
– Column 2: References one of the three standard JTAG Cell Types (BC_4, BC_2, and BC_7) that are
used for this JTAG cell in the MPC533. See the IEEE Std. 1149.1-1990, IEEE Standard Test Access
Port and Boundary-Scan Architecture document for further description of these standard cell types.
– Column 3: Lists the pin name (also called the PortID) for all pin-related cells. For JTAG control cells or
data cells that have been designated as "internal", an asterisk, is shown in this column.
– Column 4: Lists the BSDL pin function.
– Column 5: The "safe bit" column specifies the value that should be loaded into the capture (and
update) flip-flop of a given cell when board-level test generation software might otherwise choose a
value randomly.
– Column 6: The "control cell" column identifies the cell number of the control cell that is associated with
this data cell, and can disable its output.
– Column 7: The "disable value" column gives the value that must be scanned into the control cell
identified by the previous "control cell" (column 6) to disable the port named by the relevant portID.
– Column 8: The "disable result" column identifies a given signal value of the PortID if that signal can be
disabled. The values shown specifies the condition of the driver of that signal when it is disabled.
– Column 9: The "pin function" column indicates the normal system pin directionality. (– Input Only Pin,
O – Output Only Pin, I/O – Bidirectional I/O pin)
– Column 10: The pad type column describes relevant characteristics about each pad type. See the Pad
Type Keys in Note 5 above.
23.1.2
Instruction Register
The
JTAG
implementation
SAMPLE/PRELOAD, and BYPASS), and also supports the CLAMP instruction. One
additional public instruction (HI-Z) provides the capability for disabling all device output
drivers. The includes a 4-bit instruction register without parity consisting of a shift register
with four parallel outputs. Data is transferred from the shift register to the parallel outputs
during the update-IR controller state. The four bits are used to decode the five unique
instructions listed in.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
includes
Table 23-1. Instruction Decoding
Code
B3
B2
B1
0
0
0
0
0
0
0
X
1
0
1
0
0
1
0
Chapter 23. IEEE 1149.1-Compliant Interface (JTAG)
IEEE 1149.1 Test Access Port
the
public
1
B0
Instruction
0
EXTEST
1
SAMPLE/PRELOAD
X
BYPASS
0
HI-Z
1
CLAMP and BYPASS
instructions
(EXTEST,
23-5
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