Motorola MPC533 Reference Manual page 775

Maximum_Pulse_Width
17.10.3.5 Duty Cycles (0% and 100%)
The 0% and 100% duty cycles are special cases to give flexibility to the software to create
a full range of outputs. The "always set" and "always clear" conditions of the output
flip-flop are established by the value in register MPWMPULR2. These boundary
conditions are generated by software, just like another pulse. When the PWM output is
being used to generate an analog level, the 0% and 100% represent the full scale values.
The 0% output is created with a 0x0000 in register MPWMPULR2, which prevents the
output flip-flop from ever being set.
The 100% output is created when the content of register MPWMPULR2 is equal to or
greater than the content of register MPWMPERR. Thus, the width register match occurs on
counter reload. The state sequencer provides the timing to ensure that the first appearance
of a 100% value in register MPWMPULR2 causes a glitchless always-set condition of the
output flip-flop when TRSP = '0'.
Even if the output is forced to 100%, the 16-bit up counter
continues its counting and that output changes to or from the
100% value are done synchronously to the selected period.
When a PWM output period is selected to be 65536 PWM
clocks by loading 0x0000 in the period register, it is not
possible to have an 100% duty cycle output signal. In this case,
the maximum duty cycle available is of 65535/65536.
17.10.3.6 Pulse/Frequency Range Table
Table 17-25 summarizes the frequency and minimum pulse width values that can be
obtained respectively with divide-by-1 and divide-by-256 MPWMSM clock prescaler
options, while using a MIOS14 CLOCK frequency of 40 MHz, and for each MCPSM clock
divide ratios.
MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14)
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MIOS14 Pulse Width Modulation Submodule (MPWMSM)
N MCPSM N MPWMSM ²
= ---------------------------------------------------------------------------------------------------------------------------------------- -
f SYS
NOTE
NOTE
Bit_of_Resolution
( )
² 2 1
–
17-51