Motorola MPC533 Reference Manual page 1025

Chapter 23
IEEE 1149.1-Compliant Interface (JTAG)
The chip design includes user-accessible test logic that is compatible with the IEEE
1149.1-1994 Standard Test Access Port and Boundary Scan Architecture. The
implementation supports circuit-board test strategies based on this standard. An overview
of the pins requirement on JTAG is shown in Table 23-1.
TDI
TCK
TMS
JCOMP / RSTI
TDO
23.1 IEEE 1149.1 Test Access Port
The provides a dedicated user-accessible test access port (TAP) that is compatible with the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture in all but two
areas listed below. Problems associated with testing high density circuit boards have led to
development of this proposed standard under the sponsorship of the Test Technology
Committee of IEEE and the Joint Test Action Group (JTAG). The implementation supports
circuit-board test strategies based on this standard.
IEEE1149.1 Compatibility Exceptions
• The MPC533 enters JTAG mode by going through a standard device reset sequence
with the JCOMP signal asserted high. Once JTAG has been entered, the remains in
JTAG mode until another reset sequence is applied to exit JTAG mode, or the device
is powered down.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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Figure 23-1. Pin Requirement on JTAG
Chapter 23. IEEE 1149.1-Compliant Interface (JTAG)
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MPC533
TRST
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23-1