Motorola MPC533 Reference Manual page 439

12.4.3 ILBS Sequencing
The IMB interface drives the ILBS signals continuously, incrementing through a code
sequence (0b00, 0b01, 0b10, 0b11) once every clock. The IRQMUX[0:1] bits in the IMB
module configuration register select which type of multiplexing the interrupt synchronizer
will perform. The IRQMUX field can select time-multiplexing protocols for 8, 16, 24 or 32
interrupt sources. These protocols would take one, two, three or four clocks, respectively.
Table 12-3 shows ILBS sequencing. Programming IRQMUX[0:1] to 0b00 disables time
multiplexing. In this case the ILBS lines remain at 0b00 at all times. In this mode, no
interrupts from IMB modules which assert on levels 8 through 31 are ever latched by the
interrupt synchronizer. Time multiplexing is disabled during reset, and enabled as soon as
reset is released unless the reset default value is 0b00. In that case time multiplexing
remains disabled.
The timing for the scheme and the values of ILBS and the interrupt levels driven onto the
IMB IRQ lines are shown in Figure 12-5. This scheme causes a maximum latency of four
clocks and an average latency of two clocks before the interrupt request can reach the
interrupt synchronizer.
IMB CLOCK
ILBS [0:1]
IMB LVL[0:7]
Note: This diagram represents the ILBS behavior when IRQMUX[0:1] = 11
Figure 12-5. Time-Multiplexing Protocol for IRQ Signals
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
00 01
10
LVL LVL
[0:7]
[8:15]
Table 12-3. ILBS Signal Functionality
ILBS[0:1]
00 IMB interrupt sources mapped onto 0:7 levels will
drive interrupts onto IMB LVL[0:7]
01 IMB interrupt sources mapped onto 8:15 levels will
drive interrupts onto IMB LVL[0:7]
10 IMB interrupt sources mapped onto 16:23 levels will
drive interrupts onto IMB LVL[0:7]
11 IMB interrupt sources mapped onto 24:31 levels will
drive interrupts onto IMB LVL[0:7]
Chapter 12. U-Bus to IMB3 Bus Interface (UIMB)
00 01
11
LVL
LVL
LVL
24:31 0:7
16:23
Description
Interrupt Operation
10 11
12-5