Motorola MPC533 Reference Manual page 287

the middle of the high phase of GCLK2_50. EBDF determines the division factor between
GCLK1/GCLK2 and GCLK1_50/GCLK2_50.
During power-on reset, the MOCCK1, MODCK2, and MODCK3 pins determine the clock
source for the PLL and the clock drivers. These pins are latched on the positive edge of
PORESET. Their values must be stable as long as this line is asserted. The configuration
modes are shown in Table 8-1. MODCK1 specifies the input source to the SPLL (main
system oscillator or EXTCLK). MODCK1, MODCK2, and MODCK3 together determine
the multiplication factor at reset and the functionality of limp mode.
If the configuration of PITRTCLK and TMBCLK and the SPLL multiplication factor is to
remain unchanged in power-down low-power mode, the MODCK signals should not be
sampled at wake-up from this mode. In this case the PORESET pin should remain negated
and HRESET should be asserted during the power supply wake-up stage.
When MODCK1 is cleared, the output of the main oscillator is selected as the input to the
SPLL. When MODCK1 is asserted, the external clock input (EXTCLK pin) is selected as
the input to the SPLL. In all cases, the system clock frequency (freq
by the DFNH[0:2] bits in the SCCR. Note that freq
are cleared.
The TBS bit in the SCCR selects the time base clock to be either the SPLL input clock or
GCLK2. When the backup clock is functioning as the system clock, the backup clock is
automatically selected as the time base clock source.
The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the
SCCR. When the backup clock is functioning as the system clock, the backup clock is
automatically selected as the time base clock source.
When the PORESET pin is negated (driven to a high value), the MODCK1, MODCK2, and
MODCK3 values are not affected. They remain the same as they were defined during the
most recent power-on reset.
Table 8-1 shows the clock configuration modes during power-on reset (PORESET
asserted).
The MODCK[1:3] are shared functions with IRQ[5:7]. If
IRQ[5:7] are used as interrupts, the interrupt source should be
removed during PORESET to insure the MODCK pins are in
the correct state on the rising edge of PORESET.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
Chapter 8. Clocks and Power Control
Internal Clock Signals
gclk2
occurs when the DFNH bits
gclk2(max)
) can be reduced
8-9