Motorola MPC533 Reference Manual page 613

15.4.2 Freeze Operation
The FRZ1 bit in QSMCMMCR determines how the QSMCM responds when the IMB3
FREEZE signal is asserted. FREEZE is asserted when the CPU enters background debug
mode. Setting FRZ1 causes the QSPI to halt on the first transfer boundary following
FREEZE assertion. FREEZE causes the SCI1 transmit queue to halt on the first transfer
boundary following FREEZE assertion.
15.4.3 Access Protection
The SUPV bit in the QMCR defines the assignable QSMCM registers as either
supervisor-only data space or unrestricted data space.
When the SUPV bit is set, all registers in the QSMCM are placed in supervisor-only space.
For any access from within user mode, the IMB3 address acknowledge (AACK) signal is
asserted and a bus error is generated.
Because the QSMCM contains a mix of supervisor and user registers, AACK is asserted for
either supervisor or user mode accesses, and the bus cycle remains internal. If a
supervisor-only register is accessed in user mode, the module responds as if an access had
been made to an unauthorized register location, and a bus error is generated.
15.4.4 QSMCM Interrupts
The interrupt structure of the IMB3 supports a total of 32 interrupt levels that are time
multiplexed on the IRQB[0:7] lines as seen in Figure 15-2.
IMB3 CLOCK
ILBS[0:1]
IMB3 IRQ[7:0]
In this structure, all interrupt sources place their asserted level on a time multiplexed bus
during four different time slots, with eight levels communicated per slot. The ILBS[0:1]
signals indicate which group of eight are being driven on the interrupt request lines.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
00 01
10
IRQ IRQ
7:0 15:8
Figure 15-2. QSMCM Interrupt Levels
Chapter 15. Queued Serial Multi-Channel Module
00 01
11
IRQ
IRQ
IRQ
31:24 7:0
23:16
QSMCM Global Registers
10 11
15-7