Motorola MPC533 Reference Manual page 849

Writing EHV = 0 before HVS = 0 causes the current erase
sequence to ABORT. All blocks being erased must go through
another erase sequence before the UC3F EEPROM can be used
reliably.
6. Read the UC3FCTL register. Confirm PEGOOD =1.
7. Write EHV = 0 in the UC3FCTL register.
8. Write SES =0 in the UC3FCTL register.
Reset
State
S1 Normal Operation:
Normal array reads and register accesses. The
Block protect information can be modified.
S2 Erase Hardware Interlock Write:
Normal read operation still occurs. The UC3F will
accept the erase hardware interlock write. This
write may be to any UC3F array location. Accesses
to the registers are normal register accesses. A
write to UC3FCTL cannot set EHV at this time. A
write to the register is not an erase hardware
interlock write and the UC3F remains in state S2.
S3 High voltage write enable
Accesses to the registers are normal register
accesses. A write to UC3FCTL can change SES or
EHV.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
WARNING
S2
T1 T2
T6
S1
Figure 19-9. Erase State Diagram
Table 19-8. Erase Interlock State Descriptions
Mode
Chapter 19. CDR3 Flash (UC3F) EEPROM
T3
T7
S3
T4
S4
T5
T9
T10
Next
State
S2 T2 Write PE = 1, SES = 1.
S1 T1 Write SES = 0 or a reset.
S3 T3 Hardware Interlock
A successful write to any UC3F array
location is the erase interlock write. If
the write is to a register the erase
hardware interlock write has not been
done and the UC3F remains in state
S2.
S1 T6 Write SES = 0 or a reset.
S4 T4 Write EHV = 1.
UC3F Operation
T8
S5
Transition Requirement
19-27