Motorola MPC533 Reference Manual page 438

Interrupt Operation
12.4 Interrupt Operation
The interrupts from the modules on the IMB3 are propagated to the interrupt controller in
the USIU through the UIMB interface. The UIMB interrupt synchronizer latches the
interrupts from the IMB3 and drives them onto the U-bus, where they are latched by the
USIU interrupt controller.
12.4.1 Interrupt Sources and Levels on IMB
The IMB3 has eight interrupt lines. There can be a maximum of 32 levels of interrupts from
the modules on IMB bus. A single module can be a source for more than one interrupt. For
example, the QSMCM can generate two interrupts (one for QSCI1/QSCI2 and another for
QSPI). In this case, the QSMCM has two interrupt sources. Each of these two sources can
assert the interrupt on any of the 32 levels.
It is possible for multiple interrupt sources to assert the same interrupt level. To reduce the
latency, it is a good practice for each interrupt source to assert an interrupt on a level on
which no other interrupt source is mapped.
12.4.2 IMB Interrupt Multiplexing
The IMB has 10 lines for interrupt support. Eight lines are for interrupts and two are for
interrupt level byte select (ILBS). These lines will transfer the 32 interrupt levels to the
interrupt synchronizer. A diagram of the interrupt flow is shown in Figure 12-4.
Byte-enable
to IMB
2
Figure 12-4. Interrupt Synchronizer Signal Flow
Latching 32 interrupt levels using eight IMB interrupt lines is accomplished with a 4:1
time-multiplexing scheme. The UIMB drives two signals (ILBS[0:1]) with a multiplexer
select code that tells all interrupting modules on the IMB about which group of signals to
drive during the next clock. See Figure 12-5.
12-4
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IMB3 Interrupt
Byte-enables
Byte Count
Block
4
MPC533 Reference Manual
UIPEND
Register
8
[0:7]
8
[8:15]
[16:23]
[24:31]
U-bus Interrupt
Level[0:7]
U-bus
Data[0:31]
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