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IEEE 1149.1 Test Access Port
The parallel output of the instruction register is reset to all ones in the test-logic-reset
controller state.
This preset state is equivalent to the BYPASS instruction.
During the capture-IR controller state, the parallel inputs to the instruction shift register are
loaded with the CLAMP command code.
23.1.2.1 EXTEST
The external test (EXTEST) instruction selects the 520-bit boundary scan register.
EXTEST also asserts internal reset for the system logic to force a predictable beginning
internal state while performing external boundary scan operations.
By using the TAP, the register is capable of:
a) scanning user-defined values into the output buffers
b) capturing values presented to input pins
c) controlling the output drive of three-state output or bidirectional pins
23.1.2.2 SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction initializes the boundary scan register output cells
prior to selection of EXTEST. This initialization ensures that known data will appear on the
outputs when entering the EXTEST instruction. The SAMPLE/PRELOAD instruction also
provides a means to obtain a snapshot of system data and control signals.
Since there is no internal synchronization between the scan
chain clock (TCK) and the system clock (CLKOUT), there
must be provision of some form of external synchronization to
achieve meaningful results.
23.1.2.3 BYPASS
The BYPASS instruction selects the single-bit bypass register as shown in Figure 23-4.
This creates a shift register path from TDI to the bypass register and, finally, to TDO,
circumventing the 520-bit boundary scan register. This instruction is used to enhance test
efficiency when a component other than the becomes the device under test.
23-6
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1
B0 (LSB) is shifted first
NOTE
NOTE
MPC533 Reference Manual
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