Motorola MPC533 Reference Manual page 289

8.5.1 General System Clocks
The general system clocks (GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and
GCLK2_50) are the basic clock supplied to all modules and sub-modules on the MPC533.
GCLK1C and GCLK2C are supplied to the RCPU and to the BBC. GCLK1C and GCLK2C
are stopped when the chip enters the doze-low power mode. GCLK1 and GCLK2 are
supplied to the SIU and the clock module. The external bus clock GCLK2_50 is the same
as CLKOUT. The general system clock defaults to VCO/2 = 20 MHz (assuming a 20-MHz
system frequency) with default power-on reset MF values.
The general system clock frequency can be switched between different values. The highest
operational frequency can be achieved when the system clock frequency is determined by
DFNH (CSRC bit in the PLPRCR is cleared) and DFNH = 0 (division by one). The general
system clock can be operated at a low frequency (gear mode) or a high frequency. The
DFNL bits in SCCR define the low frequency. The DFNH bits in SCCR define the high
frequency.
The frequency of the general system clock can be changed dynamically with the system
clock control register (SCCR), as shown in Figure 8-5.
VCO/2 (e.g., 40 MHz)
O
The frequency of the general system clock can be changed "on the fly" by software. The
user may simply cause the general system clock to switch to its low frequency. However,
in some applications, there is a need for a high frequency during certain periods. Interrupt
routines, for example, may require more performance than the low frequency operation
provides, but must consume less power than in maximum frequency operation. The
MPC533 provides a method to automatically switch between low and high frequency
operation whenever one of the following conditions exists:
• There is a pending interrupt from the interrupt controller. This option is maskable by
the PRQEN bit in the SCCR.
• The (POW) bit in the MSR is clear in normal operation. This option is maskable by
the PRQEN bit in the SCCR.
When neither of these conditions exists and the CSRC bit in PLPRCR is set, the general
system clock switches automatically back to the low frequency.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
DFNH Divider
DFNL Divider
Figure 8-5. General System Clocks Select
Chapter 8. Clocks and Power Control
Internal Clock Signals
Normal
DFNH
O
O
General System Clock
DFNL
O
Low Power
8-11