Motorola MPC533 Reference Manual page 297

Operation Mode
Normal-low ("gear")
Deep-sleep
Power-down
8.7.3.1 Exiting from Normal-Low Mode
In normal mode (as well as doze mode), if the PLPRCR[CSRC] bit is set, the system
toggles between low frequency (defined by PLPRCR[DFNL]) and high frequency (defined
by PLPRCR[DFNH]. The system switches from normal-low mode to normal-high mode if
either of the following conditions is met:
• An interrupt is pending from the interrupt controller; or
• The MSR[POW] bit is cleared (power management is disabled).
When neither of these conditions are met, the PLPRCR[CSRC] bit is set, and the
asynchronous interrupt status bits are reset, the system returns to normal-low mode.
8.7.3.2 Exiting From Doze Mode
The system changes from doze mode to normal-high mode whenever an interrupt is
pending from the interrupt controller.
8.7.3.3 Exiting From Deep-Sleep Mode
The system switches from deep-sleep mode to normal-high mode if any of the following
conditions is met:
• An interrupt is pending from the interrupt controller
• An interrupt is requested by the RTC, PIT, or time base
• A decrementer exception
In deep-sleep mode the PLL is disabled. The wake-up time from this mode is up to 500 PLL
input frequency clocks. In one-to-one mode the wake-up time may be up to 100 PLL input
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 8-6. Power Mode Wake-Up Operation
Wake-up
Method
Software
or
Interrupt
Doze-high Interrupt
Doze-low Interrupt
Sleep Interrupt
Interrupt
Interrupt
External
Chapter 8. Clocks and Power Control
Return Time from Wake-up
Event to Normal-High
Asynchronous interrupts:
3-4 maximum system cycles
Synchronous interrupts:
3-4 actual system cycles
3-4 maximum system clocks
< 500 Oscillator Cycles
125 µs – 4 MHz
25 µs – 20 MHz
< 500 oscillator cycles + power
supply wake-up
Power-on sequence
Low-Power Modes
8-19