Motorola MPC533 Reference Manual page 1069

Table H-9. QADC64E A Queued Analog-to-Digital Converter) (continued)
Address Access
0x30 4802 S
0x30 4804 S
0x30 4806 S/U
0x30 4808 S/U
0x30 480A S/U
1
0x30 480C S/U
1
0x30 480E S/U
0x30 4810 S/U
0x30 4812 S/U
0x30 4814 – —
0x30 49FE
0x30 4A00 – S/U
0x30 4A7E
0x30 4A80 – S/U
0x30 4AFE
0x30 4B00 – S/U
0x30 4B7E
0x30 4B80 – S/U
0x30 4BFE
1
Bit 3 (SSEx) is readable in test mode only.
Table H-10. QSMCM A and B (Queued Serial Multi-Channel Module)
Address Access
0x30 5000 S
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Symbol
QADC64TST QADC64 Test Register.
QADC64INT_A Interrupt Register.
See Section 36.2.2, "QADC64E Interrupt
Register (QADCINT)," for bit descriptions.
PORTQA_A/ Port A and Port B Data.
PORTQB_A See Table 13-20 for bit descriptions.
DDRQA_A/ Port A Data and Port B Direction Register.
DDRQB_A See Table 13-20 for bit descriptions.
QACR0_A QADC64 Control Register 0.
See Table 36-8 for bit descriptions.
QACR1_A QADC64 Control Register 1.
See Table 36-8 for bit descriptions.
QACR2_A QADC64 Control Register 2.
See Table 36-12 for bit descriptions.
QASR0_A QADC64 Status Register 0.
See Table 36-8 for bit descriptions.
QASR1_A QADC64 Status Register 1.
See Table 36-15 for bit descriptions.
— Reserved
CCW_A Conversion Command Word Table.
See Table 36-18 for bit descriptions.
RJURR_A Result Word Table
Right-Justified, Unsigned Result Register.
See Section 36.2.10, "Result Word Table," for
bit descriptions.
LJSRR_A Result Word Table
Left-Justified, Signed Result Register.
See Section 36.2.10, "Result Word Table," for
bit descriptions.
LJURR_A Result Word Table
Left-Justified, Unsigned Result Register.
See Section 36.2.10, "Result Word Table," for
bit descriptions.
Symbol
QSMCM_A
(Note: Bit descriptions apply to QSMCM_B as well)
QSMCMMCR_A QSMCM Module Configuration Register.
See Table 15-7 for bit descriptions.
Appendix H. Internal Memory Map
Register
Register
Size Reset
16 S
16 S
16 U
16 S
16 S
16 S
16 S
16 S
16 S
— —
16 U
16 X
16 X
16 X
Size Reset
16 S
H-11