Integer Unit (Iu); Load/Store Unit (Lsu) - Motorola MPC533 Reference Manual

Independent Execution Units
3.4.2

Integer Unit (IU)

The IU executes all integer processor instructions (except the integer storage access
instructions) implemented by the load/store unit. The IU contains the following subunits:
• The IMUL–IDIV unit, which implements the integer multiply and divide
instructions
• The Arithmetic Logic Unit (ALU)–BFU unit, which implements all integer logic,
add, subtract, and bit-field instructions
The IU also includes the integer exception register (XER) and the general-purpose register
file.
IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU–BFU
unit can execute one instruction per clock cycle. IMUL–IDIV instructions require multiple
clock cycles to execute. IMUL–IDIV is pipelined for multiply instructions, so that
consecutive multiply instructions can be issued on consecutive clock cycles. Divide
instructions are not pipelined; an integer divide instruction preceded or followed by an
integer divide or multiply instruction results in a processor-pipeline stall. However, since
IMUL–IDIV and ALU–BFU are implemented as separate execution units, an integer divide
instruction preceded or followed by an ALU–BFU instruction does not cause a delay in the
pipeline.
3.4.3

Load/Store Unit (LSU)

The load/store unit handles all data transfer between the general-purpose register file and
the internal load/store bus (L-bus). The load/store unit is implemented as an independent
execution unit so that stalls in the memory pipeline do not stall the master instruction
pipeline (unless there is a data dependency). The unit is fully pipelined so that memory
instructions of any size may be issued on back-to-back cycles.
There is a 32-bit wide data path between the load/store unit and the general-purpose register
file. Single-word accesses can be achieved with an internal on-chip data RAM, resulting in
a two-clock latency. Double-word accesses require two clocks, resulting in a three-clock
latency. Since the L-bus is 32 bits wide, double-word transfers require two bus accesses.
The load/store unit performs zero-fill for byte and half-word transfers and sign extension
for half-word transfers.
Addresses are formed by adding the source-one register operand specified by the
instruction (or zero) to either a source-two register operand or to a 16-bit, immediate value
embedded in the instruction.
3-6
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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