Motorola MPC533 Reference Manual page 738

MIOS14 Counter Prescaler Submodule (MCPSM)
Table 17-6. MIOS14MCR Bit Descriptions (continued)
Bits Name
2 FRZ Freeze enable — The FRZ bit, while asserted, activates the MIOB freeze signal only when the
IMB3 FREEZE signal is active. The MIOB freeze signal is further validated in some submodules
with internal freeze enable bits in order for the submodule to be frozen. The MBISM continues to
operate to allow the CPU access to the submodule's registers. The MIOB freeze signal remains
active until the FRZ bit is written to zero or the IMB3 FREEZE signal is negated. The FRZ bit is
cleared by reset.
0 Ignores the FREEZE signal on the IMB3, allows MIOS14 operation.
1 Selectively stops MIOS14 operation when the FREEZE signal appears on the IMB3.
3 RST Module reset — The RST bit is always read as 0 and can be written to 1. When the RST bit is
written to 1 operation of the MIOS14 completely stops and resets all the values in the submodule.
This completely stops the operation of the MIOS14 and reset all the values in the submodules
registers that are affected by reset. This bit provides a way of resetting the complete MIOS14
module regardless of the reset state of the CPU. The RST bit is cleared by reset.
0 Writing a 0 to RST has no effect.
1 Reset the MIOS14 submodules.
4:7 — Reserved
8 SUPV Supervisor data space selector — The SUPV bit tells if the address space from (0x30 6000) to
(0x30 67FF) in the MIOS14 is accessed at the supervisor privilege level (See the address map
on Table 17-3). When cleared, these addresses are accessed at the unrestricted privilege level.
The SUPV bit is cleared by reset.
0 Unrestricted Data Space.
1 Supervisor Data Space.
9:15 — Reserved. These bits are used for the IARB (interrupt arbitration ID) field in MIOS14
implementations that use hardware interrupt arbitration. These bits are not used on MPC533.
17.7 MIOS14 Counter Prescaler Submodule (MCPSM)
The MIOS14 counter prescaler submodule (MCPSM) divides the MIOS14 clock (f
generate the counter clock. It is designed to provide all the submodules with the same
division of the main MIOS14 clock (division of f
clock signal is prescaled by loading the value of the clock prescaler register into the
prescaler counter every time it overflows. This allows all prescaling factors between two
and 16. Counting is enabled by asserting the PREN bit in the control register. The counter
can be stopped at any time by negating this bit, thereby stopping all submodules using the
output of the MCPSM (counter clock). A block diagram of the MCPSM is given in
Figure 17-7.
The following sections describe the MCPSM in detail.
17-14
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Description
). It uses a 4-bit modulus counter. The
SYS
MPC533 Reference Manual
) to
SYS
MOTOROLA