Motorola MPC533 Reference Manual page 1061

Table H-2. SPR (Special Purpose Registers) (continued)
Address Access
SPR 144 — —
SPR 147
SPR 148 —
SPR 149 —
SPR 150 —
SPR 151 —
SPR 152 — —
SPR 153
SPR 154 — —
SPR 155
SPR 156 —
SPR 157 —
SPR 158 —
SPR 159 —
SPR 268, 269 U
SPR 272 — U
SPR 275
SPR 284, 285 U
SPR 287 U
SPR 1022 U
SPR 528 S
SPR 529 S
SPR 536 S
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Symbol
CMPA — CMPD Comparator A-D Value Register.
See Table 21-20 for bit descriptions.
ECR Exception Cause Register.
See Table 21-21 for bit descriptions.
DER Debug Enable Register.
See Table 21-22 for bit descriptions.
COUNTA Breakpoint Counter A Value and Control
Register.
See Table 21-23 for bit descriptions.
COUNTB Breakpoint Counter B Value and Control
Register.
See Table 21-24 for bit descriptions.
CMPE — CMPF Comparator E-F Value Register.
See Table 21-25 for bit descriptions.
CMPG — CMPH Comparator G-H Value Register.
See Table 21-26 for bit descriptions.
LCTRL1 L-bus Support Control Register 1.
See Table 21-27 for bit descriptions.
LCTRL2 L-bus Support Control Register 2.
See Table 21-28 for bit descriptions.
ICTRL I-bus Support Control Register.
See Table 22-21 for bit descriptions.
BAR Breakpoint Address Register.
See Table 21-31 for bit descriptions.
TBL/TBU Time Base Register
See Table 3-11 and Section 6.2.2.4.2, "Time
Base SPRs (TB)," for bit descriptions
SPRG0 — General Special-Purpose Registers 0-3
SPRG3 See Table 3-15 for bit descriptions
TBL/TBU Time Base (Write Only) Register
See Table 3-14 and Section 6.2.2.4.2, "Time
Base SPRs (TB)" for bit descriptions
PVR Processor Version Register
See Table 3-14 for bit descriptions
FPECR Floating-Point Exception Cause Register
See Table 3-18 for bit descriptions
MI_GRA MI Global Region Attribute Register.
See Table 4-8 for bit descriptions.
EIBADR External Interrupt Relocation Table Base
Address Register.
See Table 4-9 for bit descriptions.
L2U_GRA L2U Global Region Attribute Register.
See Table 11-10 for bit descriptions.
Appendix H. Internal Memory Map
Register Size Reset
32 —
32 —
32 —
32 —
32 —
32 —
32 —
32 —
32 —
32 —
32 —
32 POR, H
32 —
32 POR, H
32 —
32 —
32 —
32 —
32 —
H-3