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Chapter 22
READI Module
The READI module provides real-time development capabilities for RCPU-based MCUs
in compliance with the IEEE-ISTO 5001-1999. This module provides development support
capabilities for MCUs in single chip mode, without requiring address and data signals for
internal visibility. The development features supported are program trace, data trace,
watchpoint trace, ownership trace, run-time access to the MCU's internal memory map, and
access to RCPU internal registers during halt, via the auxiliary port.
The auxiliary port, along with RCPU development features (such as background debug
mode and watchpoints) supports all software and hardware development in single chip
mode. The auxiliary port, along with (on-chip) calibration RAM, allows calibration
variable acquisition and calibration constant tuning in single chip mode, for automotive
powertrain development systems.
In this section the bit numbering in the register definitions of
tool mapped registers follows the Nexus IEEE-ISTO 5001 -
1999 bit numbering convention of MSB = bit 31 and
LSB = bit 0, unlike the MPC500 standard (MSB = bit 0 and
LSB = bit 31). The bit description tables list the bit numbering
and Nexus bit numbering.
22.0.1
Features Summary
The READI module is compliant with Class 3 of the IEEE-ISTO 5001-1999. The following
features are implemented:
• Program trace via branch trace messaging (BTM). Branch trace messaging displays
program flow discontinuities (direct and indirect branches, exceptions etc.),
allowing the development tool to interpolate what transpires between the
discontinuities. Thus static code may be traced.
• Data trace via data write messaging (DWM) and data read messaging (DRM). This
provides the capability for the development tool to trace reads and/or writes to
(selected) internal memory resources. Data trace also allows for calibration variable
acquisition in automotive powertrain development systems.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
Chapter 22. READI Module
22-1
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