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Burst Write Transfer
Figure 8–22. The Expansion Bus Master Writes a Burst of Data to the TMS320C6202
XCLKIN
XCS (input)
XCNTL (input)
XW/R (input)
XBE[3:0] (input)
XBLAST (input)
XAS (input)
XD[31:0]
XRDY (output)
The timing diagram shown in Figure 8–22 can be referenced for a visual
description of the steps required to complete a burst write initiated by an
external host and throttled by the XRDY signal.
1
2
3
Wait
C6202 latches CNTL
1 = XBISA
Write
0000 = Word
Internal src/dst addr
The boot configuration for XBLAST and XW/R: BLPOL = 0 and RWPOL = 0.
See Table 8–16 for more details.
Expansion Bus Host Port Operation
4
5
6
Ready
0 = XBD
Write
D1
D2
7
8
9
Wait
D3
D4
Expansion Bus
8-37
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